This invention relates generally to radio frequency amplifiers and more particularly to radio frequency amplifiers having a plurality of successively coupled field effect transistors arranged to provide a distributed power amplifier.
As is known in the art, radio frequency amplifiers configured as distributed amplifiers having a plurality of successively interconnected field effect transistors have been suggested to provide amplification of radio frequency signals. One problem associated with such type of amplifiers is that in certain applications the output power of the distributed amplifiers is limited over a selected band of operating frequencies.
As described in U.S. Pat. No. 4,543,535 issued to Yalcin Ayasli and assigned to the assignee of the present invention, the output power of the distributed amplifier may be considered as being limited by three constraints. The first constraint is related to the finite input voltage which can be provided to an input gate line without clipping the voltage waveform. The second constraint in output power is that the maximum total gate periphery that can be provided in a single stage limited over a particular range of operating frequencies. The third constraint in output power is related to the mismatch between the actual output impedance of each one of the field effect transistors and an optimum output impedance of such field effect transistors biased for maximum output power.
As described in U.S. Pat. No. 4,543,535, one solution to this problem that overcomes these three constraints is to capacitively coupled the gate electrode of each one of the transistors of the distributed amplifier to the input gate line via capacitors having selected capacitances, and thereby couple selected portions of the input signal to each one of the transistors. This arrangement provides an r.f. voltage divider which reduces the voltage fed to each one of the gate electrodes, thereby increasing the overall input power handling capability of the input circuit of the amplifier. Since the total input power fed to the distributed amplifier can be increased in accordance with the decreased input voltage signal provide each one of the gate electrodes, the arrangement provided a solution to the power presented by the limit on maximum input power to a FET, and furthr since the input voltage signal to each individual FET is reduced, the total device periphery of each device may be increased accordingly, to maintain the same gain for each field effect transistor and to provide a concomitant increase in the output power from each one of the transistors.
One problem, however, encountered with distributed amplifiers particular those having maximum drain periphery as is possible by providing the capacitively coupled gates shown in the above-mentioned patent is that the output power is limited particularly at the high end of the frequency band. Accordingly, a technique which improves the output power performance of distributed amplifiers would be desireable.